News

Semiconductor Engineering23h
On-Die And In-Package Interconnects
This report focuses on different interconnect structures, such as lines, vias, buses, and networks-on-chip, and how they’re ...
Semiconductor Engineering3d
Computer Architecture Extending The Von Neumann Model With A Dedicated Reasoning Unit For Native Artificial General Intelligence (TU Munich, Pace U.)
A new technical paper titled “Augmenting Von Neumann’s Architecture for an Intelligent Future” was published by researchers ...
Semiconductor Engineering4d
CMOS 2.0: Layered Logic For The Post-Nanosheet Era
What is CMOS 2.0? At its core, CMOS 2.0 is an effort to move beyond the limitations of a single monolithic die. Rather than ...
Semiconductor Engineering6d
Fault-Free Matrix for Analog Hardware (The Univ. of Hong Kong, Univ. of Oxford, Hewlett Packard Labs)
Free Analog Computing with Imperfect Hardware” was published by researchers at The University of Hong Kong, University of ...
Semiconductor Engineering4d
Engineering Reliable Heat Dissipation With Indium-Silver Thermal Interfaces
Flip chip lidded ball grid array (FCLBGA) packaging technology, which is commonly used in high-performance computing ...
Semiconductor Engineering4d
Machine Learning Tools Help Bridge Design-To-Manufacturing Gap
Despite the AI hype, ML tools really are proving valuable for leading-edge chip manufacturing. More aggressive feature ...
Semiconductor Engineering5d
Chiplet Ecosystem Slowly Emerges
Before the transition can be made from custom chiplet environments to a standardized off-the-shelf open marketplace, an ...
Semiconductor Engineering11d
A Better Path To Better 3D-IC Thermal Modeling
In an era where artificial intelligence, autonomous vehicles, and high-performance computing push the boundaries of ...
Semiconductor Engineering4d
The Rise Of Panel-Level Packaging
AI and HPC are fueling much-needed investment in panel-level tooling and processes. An insatiable demand for logic to memory ...
Semiconductor Engineering6d
Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.)
A new technical paper titled “Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems” was published by ...
Semiconductor Engineering4d
AI, Product Lifecycle Management, Market Dynamics: Q&A With Jay Vleeschhouwer Of Griffin Securities
In the world of EDA, Jay Vleeschhouwer, managing director of software research at Griffin Securities, needs no introduction.
Semiconductor Engineering6d
Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)
The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation” was published by ...